document no. 510 - 78 - 06 gennum corporation programmable analog signal processor GP520A - data sheet principle features of the preamp are the input impedance 100 k w and a gain of 14 db. the programmable filter block is composed of a low pass and high pass filter which generates a range of high and low pass corner frequencies. although the control current to this block varies linearly, linear to logarithmic conversion is performed internally in order to adjust the corner frequencies logarithmically. both filters feature a 12 db/octave rolloff and unity gain. the filters are followed by an agc block. up to 35 db of adjustable gain is provided as well as programmable threshold and release time. the attack time of the agc block remains fixed and is independent of the release time. the output current is driven into the preamp of the clipper, thus, the agc converts a voltage input into a current output and is therefore, a transconductance block. the next stage is an electronic mpo control peak clipper providing electronic clipping of the signal and setting of the maximum output level. the clipper output is also a transconductance block and drives a 40 k w resistor (r out 8 ) tied to the supply. the input of the final stage is an inverting operational amplifier. a feedback resistance of 240 k w is provided internally and this final stage is thus configured as a voltage drive output stage. the dc bias current through the receiver is also programmable. features ? programmable parameters - gain - low pass filter - high pass filter - agc threshold - release time - mpo - receiver bias voltage ? on-chip voltage regulator ? typical gain 60 db ? voltage drive output stage ? telecoil preamp functional block diagram full wave rectifier averaging circuit threshold agc v cc r f lin/log converter i ref lin/log converter lin/log converter r 2r hp filter + - preamp + - 40k r in14 10k voltage regulator r r 14 13 9 18 15 19 22 24 26 27 1 3 5 7 8 10 11 17 4 23 2 25 16 21 20 6 gnd i hp i lp i ref i rel i thresh i gain i clip i bias d out d in c out b out b in delta out c agc rect. in buffer out buffer in + - lp filter lpfb hp hpfb a out v cc v reg a in output - + r out 8 12 p gnd c comp 31 30 c clip 29 28 v bias 50k vc amp clipper all resistors in ohms, all capacitors in farads unless otherwise stated. standard packaging ? chip (136 x 110 mils) au bump circuit description the GP520A is a programmable analog signal path ic designed for use in hearing instruments. the GP520As programmable parameters are adjusted by external programming currents, such as generated by the gp521. the GP520A provides a 2.5 m a reference current for use by the gp521. sixteen settings are possible in the gp521, allowing the programmable current sink (pcs) to sink between 0 and 1.875 x i ref . the GP520A is composed of five functional blocks. the input preamp, a filter block, the agc block, mpo clipper and the output stage. revision date: may 1998 gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 web site: www.gennum.com e-mail: hipinfo@gennum.com
2 510 - 78 - 06 27 1 2 3 4 5 6 7 8 9 10 11 12 14 26 25 24 23 22 21 20 19 18 17 16 15 GP520A gnd i hp i lp i ref i rel i thresh i gain i clip i bias d out d in c out b out b in delta out c agc rect.in buffer out buffer in lpfb hp hpfb a out v cc v reg a in p gnd 13 30 29 28 tel-c tel-b 31 c comp c clip electrical characteristics all parameters are measured at t a = 25 o c all gains are calculated from equation g = 20 log ( d out/ d in) where d out and d in are appropriate voltage or current increases. all resistances are calculated according to equation r = (v p - v q ) / i cond where v p is voltage on the pad loaded with i cond current. v q - quiescent (unbias) voltage measured on the pad, (nothing connected to the pin). v p is the actual voltage measured on the pad at given condition (where p is pad number). for all graphs i ref is measured with 0.5v biased voltage on pin 16. general parameter symbol conditions min typ max units amplifier current i amp all pcs set to 15 - 600 - m a minimum voltage v cc 1.1 - - v regulator voltage (pad 13) v reg - 0.98 - v short circuit current (pad 13) i sc s1 closed - 2.0 - ma current reference (pad 16) i r - 2.5 - m a quiescent voltage on pad 14 v q14 600 - - mv quiescent voltage on pad 15 v q15 600 - - mv input resistance (pad 14) r in 14 i 14 = 0.3 m a (s2 closed)( note 1 ) - 100 - k w output swing high (pad 15) v oh v 14 = 0.8v (s3 closed)( note 1 ) 200 - - mv output swing low (pad 15) v ol v 1 = 0.4v (s3 closed) -200 - - mv max source current (pad 15) i source v 14 = 0.8v (s3, s4 closed) 30 - - m a v 15 = v q15 +100mv max sinking current (pad 15) i sink v 14 = 0.4v (s3,s4 closed) 30 - - m a v 15 = v q15 -100mv preamp voltage gain gain v 14 = v q14 10mv (s3 closed) - 14 - db note: 1. v ol = v oh = v p15 C v q15 all switches remain open unless otherwise stated in conditions column. parameter value / units supply voltage 5 v pad 3, 8, 10, 11, 13, 17 -0.1 v to v cc + 0.1 v pad 1, 15, 16, 18, 19, 22, 24, 26 -0.1 v to v reg + 0.1 v pad 4, 5, 7, 14, 20, 21, 23, 25, 27 -0.1 v to 0.7 v pad 2 v reg -0.7 v to v reg + 0.1 v absolute maximum ratings current reference regulator tests preamplifier caution class 1 esd sensitivity chip pad diagram
3 510 - 78 - 06 v reg 3? s3 v19 s2 r 2r r 13 9 18 19 22 5 7 11 21 20 6 gnd i hp i lp d out in lpfb hp hpfb v cc p gnd 12 v cc 2k2 0.6 v r in i hp 26 27 1 30 31 10k b out b agc c 68n 68n 10n 10n lin/log converter lin/log converter + - hp filter + - v reg a in v cc 2k2 v15 - + - + 1.3v s4 - + s1 s2 s3 v14 i 14 40k r in14 10k voltage regulator 14 13 9 15 5 7 11 6 gnd d out out a out v cc p gnd 12 3? 26 27 1 10k b out b agc c 68n 68n 10n 10n 31 30 + - preamp parameter symbol conditions min typ max units quiescent voltage on pad 18 v q18 - 650 - mv quiescent voltage on pad 19 v q19 - 650 - mv quiescent voltage on pad 20 v q20 - 550 - mv maximum dc current from pad 19 i hp max i hp = 0 m a ( s3 closed) -2- m a minimum dc current from pad 19 i hp min i hp =1.875 x i r (s3 closed) - 200 - na buffer gain gain v 19 = v q19 100mv (s2 closed) -0-db input resistance pad 20 r in20 i hp = i r -13-k w all switches remain open unless otherwise stated in conditions column. high pass filter fig. 2 high pass filter dc test circuit fig. 1 preamplifier and regulator test circuit all resistors in ohms, all capacitors in farads unless otherwise stated. all resistors in ohms, all capacitors in farads unless otherwise stated.
4 510 - 78 - 06 i lp s1 v cc 2k2 v reg 3? i ref r r 13 9 22 24 26 27 1 11 16 21 6 gnd i ref d out out 10k agc rect. in buffer out buffer in + - lp filter lpfb v cc p gnd 12 lin/log converter v26 - + - + v24 s2 s3 +1.3 v 0.6 v r in i lp c 68n 68n 10n 10n 57 b b in 30 31 parameter symbol conditions min typ max units quiescent voltage on pad 21 v q21 - 550 - mv quiescent voltage on pad 22 v q22 - 650 - mv quiescent voltage on pad 24 v q24 - 650 - mv quiescent voltage on pad 26 v q26 - 650 - mv maximum dc current from pad 22 i lp max i lp = 0 m a (s1 closed) - 2.0 - m a minimum dc current from pad 22 i lp min i lp =1.875 x i r (s1 closed) - 0.7 - m a output swing high (pad 26) v oh v 24 = v q24 + 100mv (s2 closed) (note 1) - 100 - mv output swing low (pad 26) v ol v 24 = v q24 - 100mv (s2 closed ) (note 1) - -100 - mv max sinking current from pad 26 i sink v 24 = 0.4v; v 26 = v q26 - 100mv 30 - - m a (s2, s3 closed) max sourcing current to pad 26 i source v 24 = 0.8v; v 26 = v q26 100mv -30 - - m a (s2, s3 closed) buffer gain gain v 26 = v q26 100mv - 0 - db input resistance (pad 21) r in21 i lp = i r -13 - k w note: 1. v oh = v ol = v p26 - v q26 all switches remain open unless otherwise stated in conditions column. low pass filter fig. 3 low pass filter dc test circuit all resistors in ohms, all capacitors in farads, unless otherwise stated.
5 510 - 78 - 06 680p v cc 2k2 2n2 3? pink noise generator 1n5 2n2 10 lin/log converter r 2r hp filter + - preamp + - 40k r in14 10k voltage regulator r r 14 13 918 15 19 22 24 26 5 7 11 21 20 gnd i hp i lp d out in buffer out buffer in + - lp filter lpfb hp hpfb a out v cc a in p gnd 12 lin/log converter 0.6 v 0.6v 6 i lp i hp 27 out b 68n tp b 10k 68n 10n 10n 1 31 30 i hp = 1.875 x i r fig. 6 low pass filter corner frequency vs i lp current (note 1) (fig.4 test circuit) notes: 1. corner frequency calculated in reference to signal at 3 khz 10k 1k 100 80 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 normalized i hp / i r current fig. 5 high pass filter corner frequency vs i hp current (note 1) (fig.4 test circuit) 10k 1k 700 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 normalized i hp / i r current fig. 4 ac test circuit for high & low pass filters corner frequency (hz) corner frequency (hz) all resistors in ohms, all capacitors in farads, unless otherwise stated.
6 510 - 78 - 06 1.3 v v cc 2k2 3? full wave rectifier threshold r f lin/log converter voltage regulator r r 14 13 9 22 24 26 27 13 57 11 23 2 25 6 gnd i rel i thresh i gain d out in delta out c agc rect. in buffer out buffer in + - lp filter lpfb a in p gnd 12 s1 10 68n v in r1=1m v reg averaging circuit v reg - 0.6 v i rel i thresh i gain 10k b out b 0.1 v o +12v lt001 - + 2 3 7 6 4 -12v 68n 10n 31 30 agc 10n parameter symbol conditions min typ max units quiescent voltage on pad 2 v q2 i thresh = i r - 400 - mv quiescent voltage on pad 3 v q3 i gain = i r x 1.875 - 700 - mv quiescent voltage on pad 23 v q23 - 500 - mv quiescent voltage on pad 25 v q25 - 500 - mv quiescent voltage on pad 27 v q27 - 600 - mv release current max (pad 1) i rel max i rel = 0 (s1 closed) - 300 - na release current min (pad 1) i rel min i rel = 1.875 x i r (s1 closed) - 30 - na input resistance (pad 25) r in25 i rel = i r -17-k w input resistance (pad 27) r in27 i 27 = i r -4-k w max transconductance (pad 26 to v o ) g max i gain = i r x 2 x 1.875 v p26 =30 mv pp - 160 - m a/v i thresh =1.875 x i r (note 1) gain range (pad 26 to v o ) gain range i thresh =1.875 x i r (note 2) - 33 - db v 26 = 25 mv pp output limiting level (pad 3) out lim i thresh = i r, i gain = 2 x 1.875 x i r - 0.7 - m a rms v 26 = 100 mv pp (note 3) limiting level range lim range i gain = i r x 2 x 1.875 (note 4) - 13 - db v 26 = 100 mv pp agc compression ratio cmp rat i thresh = i r i gain = 2 x 1.875 x i r (note 5) - 5 - notes: 1. g max = v o / (v 26 x 1m) 2. gain range = 20 log ( v o [ i gain = 2 x1.875 x i r ]/ v o [ i gain = 0]) 3. out lim = v o / 1m 10 20 log (v o [ v 26 =5.62mv rms ]/ v o [v 26 =17 . 8m v rms ]) agc control stage unless otherwise stated in conditions column all switches remain open, all current sources are 0 m a 4. lim range =20 log (v o [i thresh =1.875 x i r ] /v o [i thresh =0] ) 5. cmp rat = fig. 7 agc control stage test circuit -45dbv -35dbv all resistors in ohms, all capacitors in farads unless otherwise stated.
7 510 - 78 - 06 i thresh = 1.875 x i r in = - 63 dbv r1=100k w i gain = 3.75 x i r iinnin = 63 dbv fig. 9 agc gain vs i gain (fig.7 test circuit) input threshold (dbv) i gain = 3.75 x i r i 10 = 0 m a note: 1. switch s2 - open, s4 - closed. fig. 12 receiver bias voltage vs i bias (fig. 14 test circuit) 1 0.1 0.01 release time (s) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 normalized i rel / i r current 1 0.1 0.01 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 normalized i clip / i r current fig. 11 output swing vs i clip (fig.13 test circuit) (note 1) fig. 10 threshold level vs i thresh (fig.7 test circuit) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 normalized i thresh / i r current clip level (vp-p) 0.3 0.25 0.2 0.15 0.1 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 normalized i bias / i r current r f = 50k w v in = - 30 dbv (s3-b) -40 -50 -60 -70 fig. 8 release time vs i rel (fig.7 test circuit) 0 0.5 1 1.5 2 2.5 3 3.5 4 normalized i gain / i r current bias voltage (v) 30 20 10 0 -10 gain (db)
8 510 - 78 - 06 s1 r f =10k 2k2 3.3 v cc 13 9 5 7 8 11 4 6 i p8 s2 10 k r out 12 26 27 1 10n 1.3 v 68n 68n 10n 31 30 vc amp clipper s3 i in 10 i clip v cc b a v in parameter symbol conditions min typ max units quiescent voltage on pad 5 v q5 (s1 closed) - 550 - mv input bias current (pad 5) i bias r f1 =1m r f2 =0 w ( note 1 )- 0 - na quiescent voltage on pad 4 v q4 - 500 - mv quiescent voltage on pad 8 v q8 - 1.2 - v output swing high 1 (pad 8) v oh1 i in = +1 m a5--mv i clip = 0 m a ( note 2 ) output swing low 1 (pad 8) v ol 1 i in = -1 m a-5--mv i clip = 0 m a ( note 2 ) output clip symmetry 1 v sym 1 ( note 3 )- 1 - output swing high 2 (pad 8) v oh 2 i in = 5 m a-50-mv i clip = 1.875 x i r ( note 2 ) output swing low 2 (pad 8) v ol 2 i in = -5 m a - -50 - mv i clip = 1.875 x i r ( note 2 ) output clip symmetry 2 v sym 2 ( note 3 )- 1 - output resistance (pad 8) r out 8 i p8 = 10 m a ( s2 closed )-40-k w clipper voltage gain gain v in = 50mv pp ( s3-b )-12-db i clip =1.875 x i r (note 4) all switches remain as shown in the test circuit unless otherwise stated in conditions column. notes: 1. i bias = (v 7 C v 7 ) / 1m w r f = 1m w r f = 0 w clipper stage 3. v sym = (2v oh / ( v oh - v ol )) 4. gain = 20 log (v 8 / v 7 ) fig. 13 clipper test circuit 2. v ol = v oh = v q8 - v 8 all resistors in ohms, all capacitors in farads unless otherwise stated
9 510 - 78 - 06 10k v reg 3? r f v bias 13 9 57 10 11 17 6 gnd i bias d out d in b out b in output - + p gnd 12 v cc 2k2 +1.3 v s1 r in 17 26 27 1 68n i 10 10n 10n 68n 31 30 parameter symbol conditions min typ max units quiescent voltage on pad 17 v 17 - 1.2 - v min receiver bias voltage v rec min i bias = 0 m a (note 1) - 100 - mv max receiver bias voltage v rec max i bias = i r x 1.875 (note 1) - 300 - mv input resistance pad 17 r in17 i bias = i r - 40 - k w internal feedback resistor r f i 10 = i r - 240 - k w max sinking current (pad 11) i sink (s1 closed) - 10 - ma note: 1. v rec = v cc - v 11 all switches remain as shown in the test circuit otherwise stated in the condition column. output stage all resistors in ohms, all capacitors in farads, unless otherwise stated. fig. 14 output stage test circuit comments: 1. pin 23 and pin 4 represent virtual ground inputs. 2. if the length of the wires between the current sources and the GP520A is extensive, it may be necessary to connect an rc filter close to the appropriate GP520A pin for noise immunity. e.g. i clip GP520A 4 100k 10 all resistors in ohms, all capacitors in farads, unless otherwise stated.
10 510 - 78 - 06 6n8 v cc 680p full wave rectifier averaging circuit threshold agc vc amp clipper v cc r f lin/log converter i ref lin/log converter lin/log converter r 2r hp filter + - preamp + - 40k r in14 10k voltage regulator r r 14 13 9 18 15 19 22 24 26 27 1 35 7 10 11 17 4 23 2 25 16 21 6 + - lp filter output - + v cc 2n2 68n 50k vc 12 20 10n 30 10n 31 68n v bias 8 29 28 68n 2n2 2n2 2n2 c3 c4 1n5 c6 c5 c7 c8 c12 c9 c11 c10 2n2 t m 3u3 1u 10k c1 1k 50k mic 6n8 v cc mic + full wave rectifier averaging circuit threshold agc vc amp clipper v cc r f lin/log converter i ref lin/log converter lin/log converter r 2r hp filter + - preamp + - 40k r in14 10k voltage regulator r r 14 13 9 18 15 19 22 24 26 27 1 35 7 10 11 17 4 23 2 25 16 21 6 + - lp filter output - + r out 8 v cc 50k vc 22n 12 20 30 31 3? v bias 8 29 28 50k 680p 2n2 68n 10n 10n 68n 68n 2n2 c3 c4 1n5 c6 c5 c7 c8 c12 c9 c11 c10 c1 c2 all resistors in ohms, all capacitors in farads unless otherwise stated. fig. 15 typical application circuit all resistors in ohms, all capacitors in farads unless otherwise stated. fig. 16 typical telecoil application circuit document identification: data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that the y are free from patent infringement. ? copyright september 1989 gennum corporation. all rights reserved. printed in canada. revision notes: updated to data sheet
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